Design Verification of Complex Microprocessors

نویسندگان

  • Joon-Seo Yim
  • Chang-Jae Park
  • In-Cheol Park
  • Chong-Min Kyung
چکیده

As t h e complexity of microprocessor increases, functional verification becomes more difficult and emerges as t h e bottleneck of t he design cycle. In this paper, we suggest a functional verification methodology, especially for t he compatible microprocessor design. To guarantee t h e perfect compatibility with previous microprocessors, we developed these C models in different representation levels, a.e., Polaris, MCV(Mzcro-Code Verqfier) and StreC. An instruction behavioral level C model(Polarzs) is verified using the slowed-down PC. In t h e implementation of micro-architecture, a micro-operational level model(MCV) and RTL model(StreC), both written in C, are co-simulated with consistency checking(1PC) between these two models. The simulat ion speed of C models makes i t possible to test t h e “real-world” application programs on the C model with a software board model( VPC). To increase t h e confidence level of verifications, Profiler reports the verification coverage of t he test program, which is fed vack t o t h e automatic test prograin generator( Pandora). Restartabzlity feature also helps significantly reduce the total simulation time. Using t h e proposed verification methodology, we designed and verified the K486, an Intel 486-compatible microprocessor successfully.

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عنوان ژورنال:
  • Journal of Circuits, Systems, and Computers

دوره 7  شماره 

صفحات  -

تاریخ انتشار 1997